A reference-sampling based calibration-free fractional-N PLL with a PI-linked sampling clock generator

• Main Authors: Han, Jae-Soub, Eom, Tae-Hyeok, Choi, Seong-Wook, Seong, Kiho, Yoon, Dong-Hyun, Kim, Tony Tae-Hyoung, Baek, Kwang-Hyun, Shim, Yong
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2022
• 主題: Engineering::Electrical and electronic engineering; Calibration-Free; Fractional-N
• 在線閱讀: https://hdl.handle.net/10356/153918
• 機構: Nanyang Technological University

Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and...