Design of SRAM-based in-memory computing for machine learning applications

• Main Author: Sun, Shaofan
• Other Authors: Kim Tae Hyoung
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2021
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/154268
• Institution: Nanyang Technological University

The well-known Moore's Law is about to end after CMOS devices using 7nm process technology are widely used. It is becoming more and more difficult to improve chip performance and reduce chip cost by reducing the feature size of the device. At the same time, with the development and rise of technologies such as artificial intelligence, Internet of Things, and big data, data has grown rapidly in the form of an almost exponential explosion. The computer system of the von Neumann architecture, which has dominated the computing field for decades, has problems with storage walls and power walls, which is called the von Neumann bottleneck. The so-called storage wall problem refers to the mismatch between the speed of the computing unit and the storage unit. The speed of the former is much faster than the latter, and the speed of the storage unit has become a bottleneck affecting the calculation speed. The power wall problem refers to the frequent transmission of data between physically separated computing units and storage units that consume a lot of power consumption. In order to solve the von Neumann bottleneck problem, the compute-in-memory, which can also be called the integrated circuit of storage and calculation, has been proposed. The compute-in-memory circuit refers to a circuit that directly uses memory for data calculation by fusing data storage and calculation together, avoiding the storage wall problem and power wall problem caused by the separation of the calculation unit and the storage unit. It is clever to solves the von Neumann bottleneck of the von Neumann architecture computer. This dissertation discusses a single-bit weighted multiplication and point multiplication circuit structure based on the SRAM standard 6T cell array, which has good linearity and dynamic range. And on the basis of this structure, a compute-in-memory circuit that can complete 2bit weight calculation is proposed. Compared with the single-bit compute-in-memory circuit, this circuit sacrifices part of the linearity, however, multiplication and point multiplication operations can be completed well, and this structure has the potential to be expanded into a compute-in-memory structure for arbitrary bit weight operations.