SRAM-based in-memory computing for machine learning applications
In memory computing has become popular recently. It not only could accelerate the AI application on hardware, but also could solve the Neumann problem. In this field, digital SRAM design for machine learning has received a lot of attention due to its easy design and high accuracy characteristics. In...
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Nanyang Technological University
2022
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| Online Access: | https://hdl.handle.net/10356/156761 |
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sg-ntu-dr.10356-1567612023-07-04T17:46:55Z SRAM-based in-memory computing for machine learning applications Zhao, Yuqin Kim Tae Hyoung School of Electrical and Electronic Engineering THKIM@ntu.edu.sg Engineering::Electrical and electronic engineering In memory computing has become popular recently. It not only could accelerate the AI application on hardware, but also could solve the Neumann problem. In this field, digital SRAM design for machine learning has received a lot of attention due to its easy design and high accuracy characteristics. In this paper, a 4k weight-selective digital SRAM design is implemented with improvements on Bitcell and Adder Tree. It uses TG logic in the design to improve the speed and eliminate power consumption. The weight-Selective function is used to adapt to the different complexity of the calculation. The simulation is done by using the TSMC65LP process. The Bitcell Array is 64x64, GOPS is 409.6 and the frequency is 200MHz. Master of Science (Electronics) 2022-04-20T06:57:18Z 2022-04-20T06:57:18Z 2022 Thesis-Master by Coursework Zhao, Y. (2022). SRAM-based in-memory computing for machine learning applications. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/156761 https://hdl.handle.net/10356/156761 en application/pdf Nanyang Technological University |
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Engineering::Electrical and electronic engineering Zhao, Yuqin SRAM-based in-memory computing for machine learning applications |
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In memory computing has become popular recently. It not only could accelerate the AI application on hardware, but also could solve the Neumann problem. In this field, digital SRAM design for machine learning has received a lot of attention due to its easy design and high accuracy characteristics. In this paper, a 4k weight-selective digital SRAM design is implemented with improvements on Bitcell and Adder Tree. It uses TG logic in the design to improve the speed and eliminate power consumption. The weight-Selective function is used to adapt to the different complexity of the calculation. The simulation is done by using the TSMC65LP process. The Bitcell Array is 64x64, GOPS is 409.6 and the frequency is 200MHz. |
| author2 |
Kim Tae Hyoung |
| author_facet |
Kim Tae Hyoung Zhao, Yuqin |
| format |
Thesis-Master by Coursework |
| author |
Zhao, Yuqin |
| author_sort |
Zhao, Yuqin |
| title |
SRAM-based in-memory computing for machine learning applications |
| title_short |
SRAM-based in-memory computing for machine learning applications |
| title_full |
SRAM-based in-memory computing for machine learning applications |
| title_fullStr |
SRAM-based in-memory computing for machine learning applications |
| title_full_unstemmed |
SRAM-based in-memory computing for machine learning applications |
| title_sort |
sram-based in-memory computing for machine learning applications |
| publisher |
Nanyang Technological University |
| publishDate |
2022 |
| url |
https://hdl.handle.net/10356/156761 |
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