Design of a FPGA-based physical unclonable function

• Main Author: Ong, Andy Wei Wen
• Other Authors: Chang Chip Hong
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2022
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/158180
• Institution: Nanyang Technological University

As modern technology has advanced progressively throughout the years, things are getting increasingly digitized, for example: non-fungible tokens (NFTs) and crypto wallets. The security of these essential services and data are always at risk, where most of the time the data is stolen due to physical attacks. The security key used to access such services and data are usually stored as a password in a memory on the system. As such, hackers can obtain the security key using various tools and methods, gaining access to the personal data. Physical unclonable functions (PUFs) are emerging as promising hardware security solutions to deal with such security issues. The security key for PUFs is only generated when it is requested, therefore there is no need for a memory or storage for the security key. Popular silicon based PUFs are the Arbiter PUF (APUF) and the Ring Oscillator PUF (ROPUF). These PUFs use timing delays caused by manufacturing process variations to generate chip unique challenge-response pairs (CRPs) which act as the request (challenge) and security key (response). Due to the uniqueness of the response to each specific device, the key is extremely difficult to replicate even when using the same process, setup, and environment. Field Programmable Gate Arrays (FPGAs) are programmable hardware systems which differs from normal microprocessors used for Application Specific Integrated Circuits (ASICs) due to the FPGA’s flexibility in handling various applications as opposed to ASICs. However, the drawback of using FPGAs is the decrease in efficiency. In this project, the focus is on the design and implementation of an arbiter PUF on a FPGA. The results are then analyzed based on the evaluation metrics for PUFs.