Design of test setup for asynchronous digital signal processor

• Main Author: Chua, Qijing.
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing
• Online Access: http://hdl.handle.net/10356/15826
• Institution: Nanyang Technological University

The demand for Digital Signal Processors (DSP) and related algorithms has propelled it to be one of the fastest growing sectors of the semiconductor industry. Current state of the art digital systems are mainly synchronous in nature, relying on a global clock for synchronization among its various subsystems. Clock skew is a serious problem for high-speed circuitry as it has significant impact on performance and stability. Asynchronous systems do not have a global clock, thus eliminating the problems of clock distribution, clock skew and reducing power dissipation. However, usage of asynchronous system is limited due to a lack of automation design tools and environment. Testing procedures that rely on global clock for synchronisation cannot be used. This poses special challenges in testing and verification. In this report, a test setup was designed on Altera DE2 FPGA board to allow for testing and verification of an asynchronous chip. A DE2 board was programmed for communication between the PC and the asynchronous chip. A simulator was created on another DE2 board to characterize the properties and verify the functions of the interface board. A Windows application was created to allow instructions and data to be sent and received from the interface board. Functionality and timing simulations was performed to verify the functions and the timing constraints of the test setup. A PCB was designed, fabricated and assembled for another similar test chip, as the current chip is not fabricated yet.