A CMOS equivalent-time sampling digitizer for a direct-millimeter-wave UWB pulse doppler radar receiver implementation

• Main Author: Jaya, Gibran Limi
• Other Authors: Boon Chirn Chye
• Format: Thesis-Doctor of Philosophy
• Language: English
• Published: Nanyang Technological University 2022
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/159397
• Institution: Nanyang Technological University

In the past ten years, various radar integrated circuits (IC) have been proposed in the literature, with some already been commercialized. While a radar IC designed to operate in the 3.1 - 10.6 GHz ultra-wideband (UWB) band has low cost and power consumption advantages, crowded spectrum usage in the band gives rise to various constraints in the radar IC’s design and usage. In contrast, because of the directional operation of millimeter-wave (mm-wave) radio devices, spectrum crowding is less of an issue for a mm-wave radar device. Additionally, the radar cross sections (RCS) of radar targets, in general, increase with frequency. Together with the typically higher effective isotropic radiated power limits in mm-wave frequency bands, a mm-wave radar device can potentially be realized with a small antenna and, hence, a small form factor compared to its sub 10.6 GHz counterparts. This work aims to design a low-power digitizer capable of digitizing a mm-wave radar pulse signal in bulk complementary metal-oxide-semiconductor (CMOS) technology. The digitizer design is meant to be used to implement a CMOS mm-wave UWB pulse-Doppler radar transceiver with a direct radio frequency (direct-RF) receiver. The receiver in such a radar transceiver must process narrow pulses and allow for adequately sensitive Doppler-shift measurements. Designing the radar transceiver with a direct-RF receiver allows for it to be designed with lower power consumption because a direct-RF receiver suffers less from flicker noise than its traditional super-heterodyne or homodyne counterparts. Additionally, without an explicit down-converter circuit, a direct-RF receiver does not need a mm-wave local oscillator (LO) signal, whose generation and distribution consume a lot of power. In this work, a novel equivalent-time sampling analog-to-digital converter (ADC) architecture that can be used to design such a digitizer with acceptable attenuation level, low power consumption, and reduced input capacitance is proposed. The novel architecture is proposed assuming that the targets that are of interest to the pulse-Doppler radar under design have the characteristics of either a type I or type III Swerling target whose RCS does not fluctuate significantly within the radar’s acquisition time. At the heart of the proposed digitizer is a comparator bank whose comparators are designed for sampling and comparing a mm-wave frequency signal to some direct-current (DC) threshold values. In this work, each of these comparators is implemented as a ‘bare’ StrongARM latch circuit. Thus, a StrongARM latch circuit design capable of working with mm-wave input signals is analyzed in this work considering the circuit’s linearity, noise, input range, and input capacitance. A 4 GSa/s prototype of the proposed digitizer is designed and fabricated in a 40 nm low-power (LP) CMOS technology. The prototype is measured to be capable of digitizing signals with frequencies of up to 64 GHz while maintaining an effective number of bits (ENOB) of >3.2 bits. This performance is achieved with a power consumption of <20 mW and a modest figure of merit without needing the digitizer to be fabricated in a much more advanced CMOS technology node. It is also shown that the 60 GHz tuned amplifier circuit that is to drive the digitizer circuit can be designed with a gain that is more than enough to overcome the digitizer’s 9 dB attenuation at 60 GHz while consuming <10 mW of power. Lastly, the power consumption of a power-cycled 60 GHz UWB pulse-Doppler radar transceiver designed using the proposed digitizer is estimated assuming that the transceiver’s end-use is for implementing a radar system whose uses are for monitoring human targets located at distances of less than 3 m from the radar system with a range resolution of <3.5 cm. The prospective design is then compared with some prior-art CMOS UWB pulse radar transceiver designs reported in the literature. It is shown that the transceiver design can consume <1.75 mW when the transceiver is power cycled with a duty cycle ratio of 0.35% for a radar scan update rate of 1 kHz. The energy usage efficiency of the prospective 60 GHz UWB pulse radar transceiver design is comparable to that of prior-art UWB pulse radar transceivers that operate at a much lower frequency band.