Energy efficient neuromorphic computing circuit and architecture design

• Main Author: Pu, Junran
• Other Authors: Goh Wang Ling
• Format: Thesis-Doctor of Philosophy
• Language: English
• Published: Nanyang Technological University 2022
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/159982
• Institution: Nanyang Technological University

In recent years, fast computation, low power, and scalability are the key motivations for building SNN hardware. However, the unique features of SNN hardware have not been fully exploited, where the computation speed and energy efficiency of the SNN hardware can be improved. Firstly, this thesis presents a low-power and low-area router with a congestion-aware routing algorithm for SNN hardware. The fabricated router chip consumes 0.08 mW at 0.80 V, including IO pads and other peripherals. Secondly, this thesis proposes two versions of SNN hardware (Novena 1 and Novena 2). At 0.5 V, the measured leakage of Novena 1 chip is only 0.93 μW/core, and the energy efficiency is 4.8 pJ/SOP. In order to improve the processing speed and energy efficiency of the neuron core, this thesis proposes Novena 2, which achieves ultra-low energy consumption of 4.5 pJ/SOP. Finally, we present a low-cost, high-throughput digital hardware design for the Izhikevich model.