ADIC: anomaly detection integrated circuit in 65-nm CMOS utilizing approximate computing
In this paper, we present a low-power anomaly detection integrated circuit (ADIC) based on a one-class classifier (OCC) neural network. The ADIC achieves low-power operation through a combination of (a) careful choice of algorithm for online learning and (b) approximate computing techniques to lo...
Saved in:
Main Authors: | , , , , |
---|---|
Other Authors: | |
Format: | Article |
Language: | English |
Published: |
2022
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/160503 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Summary: | In this paper, we present a low-power anomaly detection integrated circuit
(ADIC) based on a one-class classifier (OCC) neural network. The ADIC achieves
low-power operation through a combination of (a) careful choice of algorithm
for online learning and (b) approximate computing techniques to lower average
energy. In particular, online pseudoinverse update method (OPIUM) is used to
train a randomized neural network for quick and resource efficient learning. An
additional 42% energy saving can be achieved when a lighter version of OPIUM
method is used for training with the same number of data samples lead to no
significant compromise on the quality of inference. Instead of a single
classifier with large number of neurons, an ensemble of K base learner approach
is chosen to reduce learning memory by a factor of K. This also enables
approximate computing by dynamically varying the neural network size based on
anomaly detection. Fabricated in 65nm CMOS, the ADIC has K = 7 Base Learners
(BL) with 32 neurons in each BL and dissipates 11.87pJ/OP and 3.35pJ/OP during
learning and inference respectively at Vdd = 0.75V when all 7 BLs are enabled.
Further, evaluated on the NASA bearing dataset, approximately 80% of the chip
can be shut down for 99% of the lifetime leading to an energy efficiency of
0.48pJ/OP, an 18.5 times reduction over full-precision computing running at Vdd
= 1.2V throughout the lifetime. |
---|