Digital image compression using approximate addition

• Main Authors: Balasubramanian, Padmanabhan, Nayar, Raunaq, Maskell, Douglas Leslie
• Other Authors: School of Computer Science and Engineering
• Format: Article
• Language: English
• Published: 2022
• Subjects: Engineering::Computer science and engineering; Image Processing; Approximate Computing
• Online Access: https://hdl.handle.net/10356/160718
• Institution: Nanyang Technological University

This paper analyzes the usefulness of approximate addition for digital image compression. Discrete Cosine Transform (DCT) is an important operation in digital image compression. We used accurate addition and approximate addition individually while calculating the DCT to perform image compression. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders individually. The accurate adder and approximate adders were implemented in an application specific integrated circuit (ASIC)-type design environment using a 32–28 nm complementary metal oxide semiconductor (CMOS) standard cell library and in a field programmable gate array (FPGA)-based design environment using a Xilinx Artix-7 device. Error analysis was performed to calculate the error parameters of various approximate adders by applying one million random input vectors. It is observed that the approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design parameters compared to the accurate adder. For an ASIC-type implementation using standard cells, an optimum approximate adder achieved 27.1% reduction in delay, 46.4% reduction in area, and 50.3% reduction in power compared to a high-speed accurate carry look-ahead adder. With respect to an FPGA-based implementation, an optimum approximate adder achieved 8% reduction in delay and 19.7% reduction in power while requiring 47.6% fewer look-up tables (LUTs) and 42.2% fewer flip-flops compared to the native accurate FPGA adder.