Dual-mode digital compensator design for integrated DC-DC converters

• Main Author: Wu, Tianhao
• Other Authors: Chang Joseph
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2022
• Subjects: Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/161094
• Institution: Nanyang Technological University

Inductive DC-DC converters are routinely employed in electronic devices to manage the voltage conversion from one level to another. For ease of integration, the converters are controlled using digital circuits when their loads are digital processors. To further facilitate the integration, particularly in portable or battery-operated devices, state-of-the-art converters are increasingly miniaturized by using on-chip or in-package passive components that are otherwise bulky in conventional designs. This miniaturization is typically achieved by operating the converter at high switching-frequencies (>20 MHz) such that the ensuing values of the passives are low enough (<130 nH) to translate to small physical size for integration with the converter. Nevertheless, the low inductance value and the high switching-frequency collectively render large ripple magnitude at the inductor current. One implication of this large ripple, particularly pertaining to compensator design, is the prominence of the Discontinuous Conduction Mode (DCM) as the major operating mode in high-frequency integrated converters as opposed to the Continuous Conduction Mode (CCM) in conventional converters. Hence, it is imperative that the compensator of the integrated converter supports dual-mode operation for both the CCM and the DCM, and that the DCM control algorithm is carefully designed for good stability and high efficiency of the converter. This dissertation describes the proposal and analysis of a dual-mode digital compensator design for high-frequency integrated DC-DC converters. The dual-mode compensator supports both the CCM and the DCM, is based on the Proportional-Integral-Derivative (PID) control algorithm to yield the desired damping ratio of 0.707 for a critically-damped second-order control system, which is the converter, during operation in either mode. The DCM compensator is implemented by means of a lookup table, where the pre-calculated coefficients of the compensator for different load current values are stored therein. This method simplifies the hardware complexity of the compensator, thereby mitigating the power dissipation when the load current is light (i.e., when the DCM is entered), and is achieved without compromising the system stability. The digital compensator is designed for a digitally-controlled DC-DC buck converter with the following specifications: 3.3 V input, 1.2 V output, 200 mA output current, and 50 MHz switching-frequency. To verify the performance of the compensator, the converter embodying theVI compensator is simulated using MATLAB Simulink. Simulation results show that the converter is stable in both the CCM and DCM. The load current range is from 5 mA to 200 mA, and the boundary between the CCM and the DCM is at 58 mA. In the DCM, the output settling time is reasonably fast at 0.5 ms (25 cycles of the 20 ns switching-period) for a load step of 40 mA. In both DCM and CCM, the output ripple voltage magnitude is relatively low at ±10% of the output voltage. Since the overall system is critically damped, there is no overshoot at the output voltage operating at all load ranges.