Development of a Verilog HDL model for 8051 microcontroller

• Main Author: Wu, Baichuan
• Other Authors: Jong Ching Chuen
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2022
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/162152
• Institution: Nanyang Technological University

Since the advent of Single Chip Microcomputer (SCM) in 1976, it has been widely used in many applications. The Intel 51 series SCMs are particularly popular due to its high integration, low price, strong processing power, relatively simple structure and other characteristics. With the advancement of electronic design automation and digital technology, the design method of describing system logic with hardware description language based on large scale Programmable logic devices is more and more widely adopted. A model of the 8051 microcontroller in Verilog HDL is useful for better understanding of t the composition and logic of 8051, and helpful in improving the design efficiency of practitioners in the electronic industry. The objective of this work is to model the 8051 microcontroller in Verilog HDL and to simulate the developed model to verify its functionality. In the work, modular design method is adopted. First, each functional module of the microcontroller is modelled and verified according to their functionalities. The modules are then integrated together with a RAM and a ROM IP core in Quartus and the whole model is verified for the integrity and reliability of its functions through simulation. This dissertation documents the development of the 8051 microcontroller model in Verilog HDL. The functions of the modules and their Verilog HDL models are described. The simulation results are analyzed and presented.