Design and analysis of SRAM-based PUFs for security applications

When the internet of things becomes the trend of development, our lives become more convenient with IOT. Meanwhile, the data are stored, transferred and processed in our daily devices. To protect these data, a security system by using non-volatile memory was developed. But the chip with NVM is expen...

Full description

Saved in:
Bibliographic Details
Main Author: Wang, Zhipeng
Other Authors: Kim Tae Hyoung
Format: Thesis-Master by Coursework
Language:English
Published: Nanyang Technological University 2022
Subjects:
Online Access:https://hdl.handle.net/10356/162547
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English
Description
Summary:When the internet of things becomes the trend of development, our lives become more convenient with IOT. Meanwhile, the data are stored, transferred and processed in our daily devices. To protect these data, a security system by using non-volatile memory was developed. But the chip with NVM is expensive to construct and the NVM can be hacked easily by using invasive attack. Thanks to the variations in manufacture process, the concept of Physical Unclonable Function is emerging. A lot of PUFs have been developed. And the most representative PUF is SRAM PUF because of the stable structure and low cost. SRAM is Static Random Access Memory, which is a memory component. With the investment carried on SRAM, SRAM PUF is developed. Due to the variations in the SRAM, SRAM cells should have different power-up patterns which can be used to generate the PUF response. The SRAM can be used in memory and PUF modes but they are in opposite direction: stable memory requires minimal variations and stable PUF needs the variation to be large. A lot of techniques to optimize the SRAM has been published so that SRAM can be used in both modes. The conventional 6T SRAM has disadvantages which it requires a buffer circuit to store the bits when the SRAM switches from memory to PUF and 6T SRAM only can generate one response for one cell. Based on that, a novel 8T DP SRAM is proposed. The new SRAM structure generates the response based on write conflicts instead of power-up process in 6T SRAM. This dissertation mainly invests the basics of conventional 6T SRAM and 8T DP SRAM. Based on the simulations, the results of 2 SRAM structures will be discussed.