Design of supply regulators for portable medical devices

• Main Author: Zhou, Ao
• Other Authors: Boon Chirn Chye
• Format: Thesis-Doctor of Philosophy
• Language: English
• Published: Nanyang Technological University 2022
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/163177
• Institution: Nanyang Technological University

The Internet of Things (IoT) based medical devices have gained great potential in the market recently, especially with the widespread of Covid-19 pandemic. This enables the growth of non-invasive portal medical devices and further the remote health monitoring system. Different types of sensors have different requirement for supply voltage value and power consumption. The output range of power supply should be wide enough to adjust for different applications. At the same time, a high power-supply-rejection-ratio (PSRR) is required for critical parts like local oscillator (LO) in communication system. A typical way to provide a solution is based on DC-DC converters followed by low-dropout (LDO) regulators. A silicon Complementary metal-oxide-semiconductor (CMOS) based DC-DC converter is commonly used and has high-efficiency for low output voltage applications only. Besides, an integrated LDO regulator occupies extra voltage margin which increases the difficulties for advanced process node with limited core voltage. Therefore, the focus of this thesis is to design supply regulators to meet these critical issues in portable medical devices. Firstly, a high conversion-ratio DC-DC boost converter based on Global Foundry (GF) GaN2BCDTM technology is proposed. Gallium Nitride (GaN) power devices have lower on resistance and gate capacitance compared to conventional silicon-based transistors. Besides, they can withstand high voltage which maybe risky for CMOS to withstand. By 3-D integration of GaN power devices and control circuits in a 180nm Bipolar-CMOS-DMOS (BCD) process, the parasitic inductance and capacitance can be greatly reduced. The chip is fabricated and measured. The measurement results show that it can convert voltage from 3.3 V to 70 V and has a maximum efficiency of 77.8% with an output power around 2.23 W. The total area is only 0.3×0.15 cm2 and its performance is comparable with state-of-the art works. Secondly, a mutual power-supply rejection technique (M-PSR) for quadrature LO generator is proposed. Different from traditional topology that uses an LDO stacked over the top of quadrature LO generator, the proposed work integrates a linear regulator to the load of current mode logic (CML) divider. The chip is fabricated and implemented in a 28 nm CMOS process. Measurement results indicate that the LO generator achieves a phase noise of -110.5 dBc/Hz@1MHz at the carrier frequency of 5.9 GHz and the power consumption is 1.8 mW. This work has a competitive figure-of-merit with supply sensitivity (FOMss) among state-of-the-art works.