Camouflaged circuit evaluations based on graph neural network

• Main Author: Zhang, Yifan
• Other Authors: Gwee Bah Hwee
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/164944
• Institution: Nanyang Technological University

Chip security has become an area that needs to be focused on in today's industry because it is a huge challenge to patents and will bring huge harm to the interests of chip design companies. This project is based on the optimization of the process in Dr. Ho Weng Geng's SAT TOOL. Before camouflaging the chip in Dr. Ho, it is necessary to bring the discriminating inputs obtained by the algorithm into the SAT attack to attack the circuit, find the circuit structure that can be cracked, and then camouflage it with a camouflaged gate to protect the chip. However, in this process, it takes a huge amount of time to generate discriminating inputs. Through the combination of circuit structure and GNN deep learning network, the generation efficiency is improved. The neural network of this project first performs output partition on the circuit to obtain the Sub Circuit. Convert the Sub Circuit to obtain the input circuit of the GNN network, combine the node labeling process, and then use it as input data of the GIN network to evaluate the output probability distribution, and under the guidance of the teacher signal, Loss backward continuously learns to obtain the model. Under the guidance of the model, an ideal input sequence is generated. From the experimental results, it can be known that the GNN module only needs about 4.5ms to do attack sequence generation while SAT Tool needs 224ms on average. And the elimination rate of the GNN module is much higher than that of SAT Tool.