SurgeNAS: a comprehensive surgery on hardware-aware differentiable neural architecture search

Differentiable neural architecture search (NAS) is an emerging paradigm to automate the design of top-performing convolutional neural networks (CNNs). However, previous differentiable NAS methods suffer from several crucial weaknesses, such as inaccurate gradient estimation, high memory consumption,...

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Main Authors: Luo, Xiangzhong, Liu, Di, Kong, Hao, Huai, Shuo, Chen, Hui, Liu, Weichen
Other Authors: School of Computer Science and Engineering
Format: Article
Language:English
Published: 2023
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Online Access:https://hdl.handle.net/10356/165388
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1653882023-12-15T00:55:00Z SurgeNAS: a comprehensive surgery on hardware-aware differentiable neural architecture search Luo, Xiangzhong Liu, Di Kong, Hao Huai, Shuo Chen, Hui Liu, Weichen School of Computer Science and Engineering HP-NTU Digital Manufacturing Corporate Lab Engineering::Computer science and engineering Neural Architecture Search Hardware Performance Prediction Differentiable neural architecture search (NAS) is an emerging paradigm to automate the design of top-performing convolutional neural networks (CNNs). However, previous differentiable NAS methods suffer from several crucial weaknesses, such as inaccurate gradient estimation, high memory consumption, search fairness, etc. More importantly, previous differentiable NAS works are mostly hardware-agnostic since they only search for CNNs in terms of accuracy, ignoring other critical performance metrics like latency. In this work, we introduce a novel hardware-aware differentiable NAS framework, namely SurgeNAS, in which we leverage the one-level optimization to avoid inaccuracy in gradient estimation. To this end, we propose an effective identity mapping regularization to alleviate the over-selecting issue. Besides, to mitigate the memory bottleneck, we propose an ordered differentiable sampling approach, which significantly reduces the search memory consumption to the single-path level, thereby allowing to directly search on target tasks instead of small proxy tasks. Meanwhile, it guarantees the strict search fairness. Moreover, we introduce a graph neural networks (GNNs) based predictor to approximate the on-device latency, which is further integrated into SurgeNAS to enable the latency-aware architecture search. Finally, we analyze the resource underutilization issue, in which we propose to scale up the searched SurgeNets within \textit{Comfort Zone} to balance the computation and memory access, which brings considerable accuracy improvement without deteriorating the execution efficiency. Extensive experiments are conducted on ImageNet with diverse hardware platforms, which clearly show the effectiveness of SurgeNAS in terms of accuracy, latency, and search efficiency. Ministry of Education (MOE) Nanyang Technological University Submitted/Accepted version This work is partially supported by the Ministry of Education, Singapore, under its Academic Research Fund Tier 2 (MOE2019-T2-1-071) and Tier 1 (MOE2019-T1-001-072), and partially supported by Nanyang Technological University, Singapore, under its NAP (M4082282) and SUG (M4082087). 2023-03-27T07:40:58Z 2023-03-27T07:40:58Z 2022 Journal Article Luo, X., Liu, D., Kong, H., Huai, S., Chen, H. & Liu, W. (2022). SurgeNAS: a comprehensive surgery on hardware-aware differentiable neural architecture search. IEEE Transactions On Computers, 72(4), 1081-1094. https://dx.doi.org/10.1109/TC.2022.3188175 0018-9340 https://hdl.handle.net/10356/165388 10.1109/TC.2022.3188175 4 72 1081 1094 en MOE2019-T2-1-071 MOE2019-T1- 001-072 NAP (M4082282 SUG (M4082087) IEEE Transactions on Computers 10.21979/N9/Y2TO6G © 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TC.2022.3188175. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Computer science and engineering
Neural Architecture Search
Hardware Performance Prediction
spellingShingle Engineering::Computer science and engineering
Neural Architecture Search
Hardware Performance Prediction
Luo, Xiangzhong
Liu, Di
Kong, Hao
Huai, Shuo
Chen, Hui
Liu, Weichen
SurgeNAS: a comprehensive surgery on hardware-aware differentiable neural architecture search
description Differentiable neural architecture search (NAS) is an emerging paradigm to automate the design of top-performing convolutional neural networks (CNNs). However, previous differentiable NAS methods suffer from several crucial weaknesses, such as inaccurate gradient estimation, high memory consumption, search fairness, etc. More importantly, previous differentiable NAS works are mostly hardware-agnostic since they only search for CNNs in terms of accuracy, ignoring other critical performance metrics like latency. In this work, we introduce a novel hardware-aware differentiable NAS framework, namely SurgeNAS, in which we leverage the one-level optimization to avoid inaccuracy in gradient estimation. To this end, we propose an effective identity mapping regularization to alleviate the over-selecting issue. Besides, to mitigate the memory bottleneck, we propose an ordered differentiable sampling approach, which significantly reduces the search memory consumption to the single-path level, thereby allowing to directly search on target tasks instead of small proxy tasks. Meanwhile, it guarantees the strict search fairness. Moreover, we introduce a graph neural networks (GNNs) based predictor to approximate the on-device latency, which is further integrated into SurgeNAS to enable the latency-aware architecture search. Finally, we analyze the resource underutilization issue, in which we propose to scale up the searched SurgeNets within \textit{Comfort Zone} to balance the computation and memory access, which brings considerable accuracy improvement without deteriorating the execution efficiency. Extensive experiments are conducted on ImageNet with diverse hardware platforms, which clearly show the effectiveness of SurgeNAS in terms of accuracy, latency, and search efficiency.
author2 School of Computer Science and Engineering
author_facet School of Computer Science and Engineering
Luo, Xiangzhong
Liu, Di
Kong, Hao
Huai, Shuo
Chen, Hui
Liu, Weichen
format Article
author Luo, Xiangzhong
Liu, Di
Kong, Hao
Huai, Shuo
Chen, Hui
Liu, Weichen
author_sort Luo, Xiangzhong
title SurgeNAS: a comprehensive surgery on hardware-aware differentiable neural architecture search
title_short SurgeNAS: a comprehensive surgery on hardware-aware differentiable neural architecture search
title_full SurgeNAS: a comprehensive surgery on hardware-aware differentiable neural architecture search
title_fullStr SurgeNAS: a comprehensive surgery on hardware-aware differentiable neural architecture search
title_full_unstemmed SurgeNAS: a comprehensive surgery on hardware-aware differentiable neural architecture search
title_sort surgenas: a comprehensive surgery on hardware-aware differentiable neural architecture search
publishDate 2023
url https://hdl.handle.net/10356/165388
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