Design of serial peripheral interface using System Verilog

• Main Author: Jeyaraj Rahul
• Other Authors: Meng-Hiot Lim
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/165644
• Institution: Nanyang Technological University

SPI (Serial peripheral interface) is a serial communication bus interface. The thesis aims to design an SPI peripheral per industrial standards to operate in a microcontroller environment. The design is done using System Verilog hardware description language. SPI typically uses two data lines (MISO and MOSI), one clock line, and one slave selection line for serial communication. One device acts as the master and drives the SCK clock. Other devices work as a slave and respond to the master’s requests synchronously with the master’s clock. The SPI design has the following features. It supports full-duplex, half-duplex, and simplex data transfer modes. The supported data size is 8-bit and 16-bit. The data bit order is configurable, i.e., LSB or MSB can be transferred first. It supports four modes of SCK polarity and phase. Fast data transfer is achieved using DMA. Burst data read and write supported by implementing FIFOs. Serial communication is assisted with CRC for validating the transferred data. All the above configurations and operation modes can be programmed using control registers, and HW status is accessible via status registers. An APB interface is exposed to read and write into the control and status register to work as part of a microcontroller system. The RTL is compiled using Synopsys VCS RTL compiler. The design is unit tested, and the simulated waveform is visualized using Synopsys VCS Verdi tool.