Low-capacitance solid-state transformer control using an analytic filter

• Main Authors: Sarda, Radhika, Rodriguez, Ezequiel, Yadav, Naga Brahmendra Gorla, Farivar, Glen G., Pou, Josep, Sriram, Vaisambhayana Brihadeeswara, Tripathi, Anshuman
• 其他作者: Interdisciplinary Graduate School (IGS)
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2023
• 主題: Engineering::Electrical and electronic engineering::Electric power::Production, transmission and distribution; Engineering::Electrical and electronic engineering::Power electronics; Analytic Filter; Low-Pass Filter; Solid-State Transformer
• 在線閱讀: https://hdl.handle.net/10356/166591; https://icpe-conf.org/program
• 機構: Nanyang Technological University

In the modular three-stage solid-state transformer (SST), each phase is integrated with large dc-link capacitors as energy buffers, to filter the second harmonic capacitor voltage ripple generated due to single-phase power processing. Although large dc-link capacitors reduce the coupling between stages of the SST and simplify the controller design, they compromise the reliability, safety and power density of the SST. Accordingly, a low-capacitance SST is desirable to address these challenges. To provide a high-bandwidth control for the low-capacitance SST, this paper proposes using an analytic filtering scheme rather than the low-pass filters used in conventional SST control schemes. A portion of the second harmonic power ripple in the high-voltage dc-link capacitors is processed by the SST’s dc-dc stage to facilitate the use of low capacitance. The effectiveness of the proposed control is demonstrated through a simulation study in PLECS.