Energy efficient HW design for advanced encryption standard

• Main Author: Pei, Zhangyi
• Other Authors: Goh Wang Ling
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/167708
• Institution: Nanyang Technological University

With the increase of IoT(Internet of Things), which collect and transmit millions of personal data, the demand for hardware security is increasing. Usually, Advanced Encryption Standard is used to ensure data privacy. It is complex and needs many computing power. However, the IoT’s Soc(system on chip) isn’t powerful enough to efficiently operate the algorithm. Hence, it’s necessary to design an efficient accelerator for AES. In this project, an architecture presented by engineers in A*STAR was refined. Also, a new arrangement proposed in Chapter allowed the decryption to be operated in the same encryption architecture. Additionally, a transpose module was designed as a peripheral to ensure the input data would be in the correct arrangement. The encryption module can achieve much lower standby power consumption through these attempts. Also, the accelerator can implement decryption with only increasing area by 64.1% and 132.9%.