Design of a low-power and high-performance current sense amplifier

• Main Author: Teng, Terence Sze Chun.
• Other Authors: Kong Zhi Hui
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/16778
• Institution: Nanyang Technological University

Static Random Access Memory (SRAM) have been used extensively in the market especially in product such as the computer systems, hand-phones, digital camera and other electronic devices. A SRAM is a more expensive but faster and low power hungry memory when compared to DRAM. Users mainly use the SRAM due the mentioned characteristics. Thus, building a SRAM which consume lower power, faster reading speed and smaller package size is utmost important. Prior to discussion on building the SRAM, one of the more important internal structures of the SRAM is the sense amplifier. As the sense amplifier consume substantial amount of power and is also one of the device in the SRAM that affects its reading speed. In this report, a new current-mode SRAM sense amplifier is presented. The new sense amplifier uses two cross-coupled inverters to ensure correct sensing of data stored in the memory cells. Using circuit analysis techniques and extensive simulations of existing designs, a new sense amplifier design is proposed to improve on the specifications that existing designs have. The new design is also insensitive to both bit-lines and data-lines capacitances. The method of using two cross coupled inverters being interconnected together ensures that the chances of erroneous readings are reduced. Although the proposed design is build using more transistors, it is able to produce a read process with lower sensing delays and with lower power consumption. Simulations are done based on the 1V/ 65nm CMOS technology from STMicroelectronics. In order to test the design’s robustness, varying supply voltages, working frequencies, bit-lines and data-lines capacitances are used during testing. Monte Carlo simulation is also carried out. It uses statistic and samplings to show the circuit robustness against process variation and mismatch variations. The results proved that the proposed design is more superior to the existing designs.