Design of low-voltage low-power low-noise folded-cascode CMOS op-amp with class AB output stage

• Main Author: Ng, Chen Hui
• Other Authors: Siek Liter
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/167789
• Institution: Nanyang Technological University

The objective of this project was to design a low-voltage, low-power, low-noise operational amplifier (op-amp) that is capable to provide an output drive of 10mA load current, and a rail-to-rail output and producing gain bandwidth product of more than 50MHz, in this project GF-55nm process technology was used with supply voltage of 1.8V. This project involves the design of a two-stage op-amp that consists of a folded cascode amplifier with a single ended output connected to the class AB output stage that uses translinear loop for biasing. To ensure the op-amp receives a constant bias voltage that will not be affected by process, temperature, and voltage supply variation, a constant transconductance (gm) biasing circuit with start-up circuitry was designed to provide reference voltage for the op-amp. The challenge in this project was to the design the folded cascode amplifier, as all the transistors must be in the saturation region and the design of the class AB output stage, this includes understanding the working principle in order to design the aspect ratio of the transistors in the translinear loop and ensuring the translinear loop was balanced. The op-amp designed in this project have achieved 86.663dB of open loop gain and 51.2643° of phase margin at unity gain bandwidth of 50.0093MHz.