Power- and area-efficient analog-to-digital conversion for in-memory computing
In-memory computing is an emerging trend in Industrial Revolution 4.0 that focuses in artificial intelligent and machine learning. By moving the computation to the edge, in-memory computing reduces energy consumption and data size that needs to be processed further. To enable an efficient in-memory...
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| Format: | Final Year Project |
| Language: | English |
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Nanyang Technological University
2023
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| Online Access: | https://hdl.handle.net/10356/167799 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | In-memory computing is an emerging trend in Industrial Revolution 4.0 that focuses in artificial intelligent and machine learning. By moving the computation to the edge, in-memory computing reduces energy consumption and data size that needs to be processed further. To enable an efficient in-memory computing, analog-to-digital converters (ADC) are required to have high linearity, low power, and low area to store the computed data in digital form.
The ADC used in this report is based on monotonic successive approximate register (SAR) that has been reported to have low switching power consumption and low area. This project further lowers the area and power consumption by reducing the resolution from 10-bit to 8-bit. The ADC is designed and simulated using TSMCn65LP CMOS technology node. Simulation results show the performance of 100MS/s with power consumption of 0.162mW |
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