A fully integrated low dropout regulator for partial discharge detection applications
The power management unit, such as the low dropout regulator (LDO), plays an important role in the integration of the DAQ chips designed for detecting the partial discharge events in the power systems. A suitable LDO in this application should be capable of providing high-quality supply voltage over...
Saved in:
Main Author: | |
---|---|
Other Authors: | |
Format: | Thesis-Master by Coursework |
Language: | English |
Published: |
Nanyang Technological University
2023
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/169197 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
id |
sg-ntu-dr.10356-169197 |
---|---|
record_format |
dspace |
spelling |
sg-ntu-dr.10356-1691972023-07-08T05:40:16Z A fully integrated low dropout regulator for partial discharge detection applications Chen, Hanlin Zheng Yuanjin School of Electrical and Electronic Engineering YJZHENG@ntu.edu.sg Engineering::Electrical and electronic engineering::Integrated circuits The power management unit, such as the low dropout regulator (LDO), plays an important role in the integration of the DAQ chips designed for detecting the partial discharge events in the power systems. A suitable LDO in this application should be capable of providing high-quality supply voltage over a wide load range while making fast responses against load variations. However, due to stability issues, it is often challenging for the fully integrated regulator design to achieve both features simultaneously. Therefore, in this dissertation, a flipped voltage follower (FVF) based LDO with a novel pole-tracking frequency compensation technique and transient enhancing structure is proposed to overcome these obstacles. The suggested FVF-LDO is built in TSMC 65 nm process with a 1 V power supply and 200 mV dropout voltage. This regulator exhibits a 95 uA to 122 uA quiescent current when supporting the load current ranging from 0.1 mA to 100 mA. With the compensation topology, an over 60 degree phase margin is obtained across the entire load range. And in full load operation, a low-frequency power supply rejection (PSR) of -59 dB and a 0.85 mV/V line regulation are achieved with a 100 pF on-chip capacitor. Furthermore, the proposed LDO presents 88 mV voltage displacement for the maximum load variation with 100 ns edge time and can settle to 1% accuracy within 640 ns with a 40 MHz unity gain bandwidth. Master of Science (Electronics) 2023-07-06T02:42:15Z 2023-07-06T02:42:15Z 2023 Thesis-Master by Coursework Chen, H. (2023). A fully integrated low dropout regulator for partial discharge detection applications. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/169197 https://hdl.handle.net/10356/169197 en application/pdf Nanyang Technological University |
institution |
Nanyang Technological University |
building |
NTU Library |
continent |
Asia |
country |
Singapore Singapore |
content_provider |
NTU Library |
collection |
DR-NTU |
language |
English |
topic |
Engineering::Electrical and electronic engineering::Integrated circuits |
spellingShingle |
Engineering::Electrical and electronic engineering::Integrated circuits Chen, Hanlin A fully integrated low dropout regulator for partial discharge detection applications |
description |
The power management unit, such as the low dropout regulator (LDO), plays an important role in the integration of the DAQ chips designed for detecting the partial discharge events in the power systems. A suitable LDO in this application should be capable of providing high-quality supply voltage over a wide load range while making fast responses against load variations. However, due to stability issues, it is often challenging for the fully integrated regulator design to achieve both features simultaneously. Therefore, in this dissertation, a flipped voltage follower (FVF) based LDO with a novel pole-tracking frequency compensation technique and transient enhancing structure is proposed to overcome these obstacles.
The suggested FVF-LDO is built in TSMC 65 nm process with a 1 V power supply and 200 mV dropout voltage. This regulator exhibits a 95 uA to 122 uA quiescent current when supporting the load current ranging from 0.1 mA to 100 mA. With the compensation topology, an over 60 degree phase margin is obtained across the entire load range. And in full load operation, a low-frequency power supply rejection (PSR) of -59 dB and a 0.85 mV/V line regulation are achieved with a 100 pF on-chip capacitor. Furthermore, the proposed LDO presents 88 mV voltage displacement for the maximum load variation with 100 ns edge time and can settle to 1% accuracy within 640 ns with a 40 MHz unity gain bandwidth. |
author2 |
Zheng Yuanjin |
author_facet |
Zheng Yuanjin Chen, Hanlin |
format |
Thesis-Master by Coursework |
author |
Chen, Hanlin |
author_sort |
Chen, Hanlin |
title |
A fully integrated low dropout regulator for partial discharge detection applications |
title_short |
A fully integrated low dropout regulator for partial discharge detection applications |
title_full |
A fully integrated low dropout regulator for partial discharge detection applications |
title_fullStr |
A fully integrated low dropout regulator for partial discharge detection applications |
title_full_unstemmed |
A fully integrated low dropout regulator for partial discharge detection applications |
title_sort |
fully integrated low dropout regulator for partial discharge detection applications |
publisher |
Nanyang Technological University |
publishDate |
2023 |
url |
https://hdl.handle.net/10356/169197 |
_version_ |
1772825363143983104 |