Ternary full adder designs employing unary operators and ternary multiplexers

• Main Authors: Jaber, Ramzi A., Haidar, Ali M., Kassem, Abdallah, Zahoor, Furqan
• Other Authors: School of Computer Science and Engineering
• Format: Article
• Language: English
• Published: 2023
• Subjects: Engineering::Computer science and engineering; Logic Design; Nanoscale Devices
• Online Access: https://hdl.handle.net/10356/169232
• Institution: Nanyang Technological University

The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary operator gates with two voltage supplies (Vdd and Vdd/2) to reduce the transistor count and energy consumption. In addition, this paper proposes two 4-trit Ripple Carry Adders (RCA) based on the two proposed TFA1 and TFA2; we use the HSPICE simulator and 32 nm CNFET to simulate the proposed circuits under different voltages, temperatures, and output loads. The simulation results show the improvements of the designs in a reduction of over 41% in energy consumption (PDP), and over 64% in Energy Delay Product (EDP) compared to the best recent works in the literature.