Low power SRAM-based computing-in-memory design
This paper outlines Computing-in-memory (CIM) technology's significance in overcoming memory wall challenges posed by traditional Von Neumann architecture. Its adaptability extends to diverse emerging applications, boosting energy efficiency and data processing speed. This study seeks to affirm...
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| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2023
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| Online Access: | https://hdl.handle.net/10356/170672 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This paper outlines Computing-in-memory (CIM) technology's significance in overcoming memory wall challenges posed by traditional Von Neumann architecture. Its adaptability extends to diverse emerging applications, boosting energy efficiency and data processing speed. This study seeks to affirm low-power SRAM-based CIM's functionality, it introduces and investigates the traditional 6T SRAM and an innovative 8T SRAM bitcell, functioning within a low-power range. Testbenches validate read and write functions and extend their utility to MAC operations. Subsequent simulations focus on stability and power consumption as well as supply voltage's impact. Results highlight the novel 8T SRAM bitcell's superiority in stability due to decoupled read and write functions, accompanied by a slight power consumption increase. Furthermore, a 64-bit memory array is built, the MAC operation within a single array column is achieved. |
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