A monotonic asynchronous full adder

• Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas L.
• Other Authors: School of Computer Science and Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2023
• Subjects: Engineering::Computer science and engineering::Hardware; Engineering::Electrical and electronic engineering::Integrated circuits; Engineering::Electrical and electronic engineering::Electronic circuits; Asynchronous Circuits; Arithmetic Circuits; Low Power Design; Digital Circuits; Digital Logic Design; High Speed
• Online Access: https://hdl.handle.net/10356/172133
• Institution: Nanyang Technological University

This paper presents a new input-output mode asynchronous full adder that is monotonic and early output type. In a monotonic asynchronous circuit, the intermediate outputs and primary outputs experience similar signal transitions as the primary inputs for the application of data and/or spacer. The proposed full adder exhibits monotonicity for processing data and spacer. The full adder employs dual-rail encoding for inputs and outputs and corresponds to return-to-zero handshaking. The early output nature of the proposed full adder could facilitate the production of sum and carry outputs based on the adder inputs without having to wait for the carry input when the spacer is supplied. When incorporated in a ripple carry adder (RCA) structure, the proposed full adder enables reductions in all the design metrics viz. cycle time, area, and total power dissipation compared to existing gate-level asynchronous full adders. Compared to the best of the existing high-speed asynchronous full adders, the proposed full adder enables a 10.4% reduction in cycle time and a 15.8% reduction in area without any power penalty when incorporated in a 32-bit RCA, for implementation using a 28-nm CMOS technology. In terms of power-cycle time product, which is representative of energy, the proposed full adder enables an 11.8% reduction.