Graph-based analysis for hardware obfuscation through logic locking

• Main Author: Huang, Erdong
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2023
• Subjects: Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/172427
• Institution: Nanyang Technological University

Global distribution of Integrated Circuit (IC) supply chain has raised concerns on security threats, such as insertion of hardware trojan, Intellectual Property (IP) piracy, and over-production. Investigation into manufactured IC chips and obfuscation on IP designs are two effective approaches to address these concerns. For the investigation into manufactured IC chips, in this paper, we proposed a standard cell recognition process, which is fully automated and with 100% accuracy. For obfuscation on IP designs, we made our contributions by revealing the vulnerability of a recently proposed Logic Locking (LL) scheme, D-MUX, using our RNN (LSTM)-based models. Testing is conducted on the ISCAS-85 benchmark circuits. Comparisons are made across different components of the node encoding. With the most comprehensive node encoding, our model successfully predicts D-MUX key values at up to 98% accuracy.