Design of a 40nm CMOS transconductance amplifier for low-dropout regulator

• Main Author: Jiang, Haochen
• Other Authors: Chan Pak Kwong
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering
• Online Access: https://hdl.handle.net/10356/173428
• Institution: Nanyang Technological University

Modern portable and high-performance electronic devices place higher limits on power consumption and space of the power management system. LDO (Low Dropout) regulator is an important part of the power management system to provide accurate and stable voltage output to the load device. This project proposes a capacitorless LDO regulator design with dynamic cascode biasing transconductance amplifier based on TSMC 40nm process. A low impedance loading network with overshoot suppression is used to allow stable operation within a load between 0uA and 50mA. Simulation results show that the proposed LDO regulator has a quiescent current of 12.52μA at 0 load current, a maximum overshoot/undershoot of 90mV, and a settling time of less than 1.8μs. Compared to conventional transconductance amplifier based LDO regulator, it is faster by about 2.6 times and the maximum transient voltage variation is reduced by 141mV.