Logic locking satisfiability evaluation based on machine learning techniques

• Main Author: Han, Yifei
• Other Authors: Lin Zhiping
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering
• Online Access: https://hdl.handle.net/10356/173544
• Institution: Nanyang Technological University

The globalization of the Integrated Circuit (IC) supply chain has led to numerous security challenges, particularly with respect to untrustworthy chip manufacturers and the protection of intellectual property. This scenario underscores the need for robust logic obfuscation solutions to mitigate these risks. Despite this, Boolean Satisfiability (SAT) attacks and related methods can nearly breach all advanced logic obfuscation techniques. This is especially true for logic locking circuits with intricate configurations, like large multipliers, which present significant difficulties to SAT attacks. This dissertation investigates methods to improve the efficiency of SAT attacks on such multiplier circuits. We introduce a preprocessing approach for circuits, which involves decomposing multiplier circuits into several logic cones. By examining the number of shared logic locks in each cone, we apply clustering algorithms to segment these cones into multiple "highly cohesive, lowly coupled" sub-circuits. These are then sequentially decrypted using an iterative attack methodology. In experiments conducted on the C6288 circuit from the ISCAS-85 benchmark, we compared the traditional SAT attack algorithms with our enhanced SAT attack approach. The findings reveal that the optimized attack algorithm reduces attack duration by an average of 70%, significantly increasing efficiency.