A sizing approach for optimizations of cascode low-noise amplifier with inductive source degeneration

This thesis illustrates a single-ended cascode low-noise amplifier (LNA) topology with inductive source degeneration, which achieves dual-band coverage through a switchable output impedance matching network. The study focuses on theoretical analysis of critical performances of the LNA including the...

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Bibliographic Details
Main Author: Bao, Hongyu
Other Authors: Zhang Yue Ping
Format: Thesis-Master by Coursework
Language:English
Published: Nanyang Technological University 2024
Subjects:
Online Access:https://hdl.handle.net/10356/173599
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Institution: Nanyang Technological University
Language: English
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Summary:This thesis illustrates a single-ended cascode low-noise amplifier (LNA) topology with inductive source degeneration, which achieves dual-band coverage through a switchable output impedance matching network. The study focuses on theoretical analysis of critical performances of the LNA including the gain, noise performance and linearity, and an optimized LNA design is then proposed based on the analysis. As a measure of the gain, the analytical expression of the S-parameter |S21| is derived through small-signal analysis, which is found to be determined by the unity gain frequency of the LNA and the parasitic resistance of the RF choke. The noise figure/factor is also derived analytically through the two-port noise theory and small-signal analysis, which takes the transistors and the parasitic resistance of the gate inductor and the RF choke into consideration. A sizing method of the transistor channel width and the external capacitor with a fixed drain current is proposed to find the optimum noise figure with a sufficiently high |S21|. To evaluate the linearity, the IIP3 point is found to be relevant with the gate biasing voltages of all transistors and the total output impedance of the LNA. The accuracy of the theoretical analysis has been verified with simulations, and a sizing approach to optimize the LNA performance is suggested based on the theoretical analysis. A design flow to have an optimized LNA performance based on the theoretical study is suggested to have a high |S21| first, then a low noise figure and finally a high IIP3 point. A circuit design using bulk RF CMOS process based on the proposed design flow is demonstrated, which is simulated to have |S21| over 22.5 dB, minimum |S11| and |S22| of approximately -20 dB, |S12| lower than -37 dB, noise figure lower than 0.65 dB and IIP3 point about -6 dBm at the targeted frequencies of 1.8 GHz and 2.0 GHz.