Comparator verification based on universal verification methodology

• Main Author: Qiao, Yunkai
• Other Authors: Chang Chip Hong
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering
• Online Access: https://hdl.handle.net/10356/173762
• Institution: Nanyang Technological University

As Integrated Circuit (IC) technology and SoC design continuously advance, the scale and complexity of IC chip designs are steadily increasing. Verification IP plays a crucial role in automating test stimulus generation, data comparison, and coverage statistics. Its integration within the SoC system-level verification environment is pivotal, which significantly enhances SoC verification efficiency and lessens the workload for verification personnel. UVM stands as the latest verification methodology with robust capabilities and advantages. This dissertation focuses on the comparator, a critical module of MCU. A highly reusable verification platform environment based on UVM theory is constructed. It effectively enhances the practicality of the verification IP. In this project, the main tasks include: (1) Conducting an in-depth study of the comparator module, analyzing its functional characteristics, and decomposing the functional test points for DUT. (2) Completing the development of the UVM verification platform, as well as designing and implementing the overall architecture of the UVM verification platform based on the verification plan. (3) Executing functional testing and analyzing test results for the comparator module; running and passing all testcases followed by regression testing; and ultimately gathering coverage data to achieve a 100% overall code coverage and 100% functional coverage. (4) Running AMS simulation for the comparator; simultaneously conducting joint simulations with other modules with mixed signals.