Digital computing-in-memory design for neural networks

• Main Author: Cheng, Guanyu
• Other Authors: Kim Tae Hyoung
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Neural network
• Online Access: https://hdl.handle.net/10356/173845
• Institution: Nanyang Technological University

With the rapid development of artificial intelligence application technology, a large amount of data transmission between the central processor and the storage circuit is recognized as the biggest bottleneck in the current traditional von Neumann computer architecture. As one of the most successful algorithms currently used for image recognition in the field of artificial intelligence, deep neural networks require a large number of multiplication and addition operations (MAC) on input data and weight data. Computing-in-Memory, the CIM circuits can not only support the general read and write operations of memory circuits, but also can perform a variety of computing operations, thus greatly reducing the amount of data movement.And further improve the energy consumption efficiency of the system. New memories and in-memory computing circuits have broad application prospects in energy-efficient artificial intelligence processors, Internet of Things terminal equipment, smart homes and smart city systems, and deserve continued in-depth research. This article first summarizes and analyzes the development origin and typical architecture of in-memory computing circuits. It mainly includes the classification of memory circuits and general read and write operations, bottleneck analysis of von Neumann architecture, an overview of deep neural network algorithms, and early in-memory computing circuits. Advantages and Disadvantages of Computational Research Work. Then this paper proposes a Bit Serial Computation in-memory computing unit with high word precision and reconfigurability to address the challenges in the design of energy-efficient in-memory computing circuits. And use the 65nm process for testing to verify the in-memory computing circuit design