Single-event-effects on a flash FPGA for satellites

• Main Author: Fang, Ao
• Other Authors: Chang Joseph
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Anti-irradiation; Single-event effect; Single-event upset; Flash FPGA
• Online Access: https://hdl.handle.net/10356/173989
• Institution: Nanyang Technological University

The space industry has now evolved from “Traditional Space” to “New Space”. Traditional Space involves large geostationary satellites embodying mostly space grade electronics while New Space involves small Low-Earth-Orbit satellites embodying mostly Commercially-Off-The-Shelf (COTS) electronics. However, most COTS electronics, such as the COTS Field Programmable Gate Array (FPGA), typically suffer from radiation effects in space, specifically Single-Event Effects (SEEs) which may render mission failure. The specific SEEs include Single-Event-Latchups (SELs) and Single-Event-Upsets (SEUs). In this dissertation, we experimentally investigate the Microsemi Flash FPGA to ascertain its susceptibility or resistance to SSEs. The primary hardware elements of our investigations are the programmable logic unit (VersaTiles) and the block memory BRAMs of the said FPGA, which are sensitive to SEEs and have the widest distribution range (present in numerous areas or sectors throughout the logical structure), in this type of FPGA. Two different test methods are proposed and completed using the existing SEE test system. The 86Kr beam and 209Bi beam are provided by HIRFL. These beams were utilized to subject the system to controlled radiation environments, facilitating the assessment of SEEs within the tested hardware components or devices. From our experiments, the Flip cross sections, which represent the vulnerability of specific components within the programmable logic unit and block memory of the tested FPGA to SEEs, are successfully obtained through the beam experiments. It is found that the turn-over cross-section of the FPGA sequential logic unit has no significant relationship with the operating frequency of the system, indicating that the vulnerability of the sequential logic unit to SEEs remains consistent regardless of variations in the system’s operational frequency. The Flipping rules of different types of D Flip-Flop, which describe their specific responses to SEEs, are thoroughly analyzed, and it is observed that the 0 1 Flip and 1 0 Flip have different flipping rules, which imply distinct alterations or changes in the state of the flip-flops triggered by radiation-induced events.