40MHz crystal oscillator design and simulation

• Main Author: Zong, Enze
• Other Authors: Siek Liter
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Crystal oscillator; Single-ended pierce structure; Phase noise; Wireline transceiver
• Online Access: https://hdl.handle.net/10356/174528
• Institution: Nanyang Technological University

In recent years, as the advancing of the wireline communication, the demand for low noise, and highly integrated crystal oscillators is rapid growing. Fully integrated on-chip low- noise crystal oscillators (XO), utilizing switched-capacitor trimming arrays, can overcome frequency drift with temperature and time while meeting the wireline transceiver’s requirements for frequency accuracy. Therefore, crystal oscillators, with their ease of integration and cost-effectiveness, hold significant market potential as alternatives to expensive off-chip crystal oscillators. The crystal oscillator, serving as a crucial circuit in the front end of the wireline transceiver, directly influences the overall performance of the transceiver, including specifications such as phase noise. This thesis presents a highly integrated, low-noise single-ended crystal oscillator design with programmable gm cell amplifier and switched-capacitor via TSMC N3E process, for a precise reference clock signal to the PLL in the wireline transceiver. The proposed crystal oscillator operates at a frequency of 40MHz. Simulation results indicate that the maximum power consumption under stable operating conditions is 2.43mW. The worst phase noise at 10 kHz, 1 MHz, and 20 MHz is -127dBc/Hz, -144dBc/Hz, and -151dBc/Hz, respectively. The frequency tuning range is approximately 300 ppm. Over a temperature range of -40 °C to +125 °C, the frequency offset is within ±10 ppm after trimming.