Cryogenic temperature resilient digital circuit design

• Main Author: Rajagopal Karthik
• Other Authors: Goh Wang Ling
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Cryogenic; Quantum computing; CMOS
• Online Access: https://hdl.handle.net/10356/174791
• Institution: Nanyang Technological University

Electronics at cryogenic temperatures, which are now widely used for Quantum computing application, require very low power operation. Several methods such as using different fabrication technologies, choosing appropriate logic design styles have proven to improve on power saving. However, the mentioned methods are effective only up to temperature levels greater than 100 K. As the temperature is reduced close to 20 mK, many non-ideal characteristics, including threshold voltage variation, effect of width and length on threshold voltage, mobility, leakage and so on, experience a drift from the usual characteristic trend followed at lower temperatures. Since the direct utilization of the existing digital design at cryogenic temperatures is not possible, there is a demand for design which can include all the necessary compensation mechanism to obtain similar functionality as in room temperature (300K). The compensated design must not only restore the original functionality, but must also satisfy the primary objective of low power consumption. The CMOS design, at any point of circuit operation (transient or steady state), must always stay within the allowed limit of power dissipation (which is usually few microwatts). This work presents a method to reduce the threshold voltage in order to reduce power consumption in a 28 nm bulk silicon technology taking into consideration performance aiming at minimal circuit modifications. The work also discusses the changes in the above mentioned non-ideal variations for different biasing methods chosen in the proposed design using standard digital logic blocks.