Simulation of 1T1R(one-transistor one RRAM) memory cell

• Main Author: Shi, Quan
• Other Authors: Chen Tupei
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; RRAM; 1T1R
• Online Access: https://hdl.handle.net/10356/175575
• Institution: Nanyang Technological University

The Von Neumann architecture of traditional storage and computing separation limits the progress in achieving high-performance computing capabilities, and memristor, as the fourth passive fundamental component in circuity, has the characteristics of low power dissipation, nanometer dimension, easy for integration, and non-volatility. Resistive random access memory (RRAM), as a new storage technology, has received widespread attention and in-depth research. It can avoid the time and energy overhead of repeatedly moving data between storage and computation,eliminating the "Storage wall" and "Power wall" problems in traditional computation systems, meet the current and future electronic memory needs for high-density information storage and high-performance computing, and has the potential to be used in application scenarios where neuromorphic computing and storage computing merge. The 1T1R (single transistor single RRAM) structure achieves efficient storage and access functions through the combination of transistor selectors and RRAM devices. It can compactly arrange a large number of memory units on the chip to achieve high-density memory integration, laying a solid foundation for building future memory computing architecture. This dissertation first reviewed the basic concepts of RRAM, including its structure, working principle and conduction mechanism, and introduced the compact model developed by Stanford University. Based on this model, two methods were used to conduct simulation in LTspice. Finally, TSMC 0.18µm CMOS n-channel MOSFET and RRAM models were utilized to construct a 1T1R memory unit circuit. The simulation involved analyzing the IV characteristics and transient response of the 1T1R unit, as well as testing the read and write functions of the memory unit.