Design of a low-voltage CMOS comparator

• 主要作者: Lai, Ye Sen
• 其他作者: Chan Pak Kwong
• 格式: Final Year Project
• 語言: English
• 出版: Nanyang Technological University 2024
• 主題: Engineering
• 在線閱讀: https://hdl.handle.net/10356/176098

In the realm of designing Integrated Circuit (IC), the low-voltage Complementary Metal-Oxide Semiconductor (CMOS) comparator is an essential building block. There are a few examples of the numerous applications such as oscillators, threshold detectors, control systems, Digital-to-Analog Converter (DAC), and Analog-to-Digital Converter (ADC) are frequently used in the workplace. It is desirable to develop a comparator that can run at low voltage since the IC design industry places a higher priority on portability and low power consumption. Even though various comparator circuit designs have been proposed, the CMOS comparator with low-power features is still a very challenging topic in the realm of IC design. In this report, the CMOS comparator circuit operates at a 0.4V power supply whilst incorporating a current source which aims to compensate the effect of propagation delay caused by the increase in temperature. This comparator is then used in the comparator-based oscillator circuit. The propagation delay caused by PVT variations in the comparator-based oscillator circuit can be compensated by adding an Addition-based current source and a PTAT current source. As a result, the low-temperature performance increased by 21.85 % and the high-temperature performance increased by 39.44 %.