A 99.82-dB SNDR 10kHz-BW second-order discrete-time ∆ modulator with enhanced noise-coupling and stage-sharing technique

• Main Author: Lu, Jiaju
• Other Authors: Goh Wang Ling
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Engineering; Delta-sigma modulator; High-resolution; Analog-to-digital convertor; Noise coupling
• Online Access: https://hdl.handle.net/10356/176221
• Institution: Nanyang Technological University

Analog to digital converter (ADC) serves as the vital junction that bridges the physical world and the digital realm. Among all types of ADCs, the Delta-Sigma ADC (DS ADC) stands out with its incomparable high-resolution thanks to its effective oversampling and noise shaping effect, securing its placing in various fields such as Internet-of-things (IoT) sensors, acoustic signal processing, biomedical devices, and instrumentations. However, modern applications, especially those powered by batteries, require not only high-bit accuracy but also excellent energy efficiency to prolong the runtime of the devices. In this context, the power-hungry delta- sigma modulator (DSM) in the DS ADC becomes a burden that limits its progress in power- sensitive applications. In this thesis, the high-resolution DSM will be studied with a focus on low-power operation and usability. The system and circuit design considerations for high-resolution and low-power DSMs will be reviewed, respectively. A second-order noise-coupling (NC) DSM with stage- sharing design and noise transfer function (NTF) enhancement is demonstrated in the thesis. The proposed DSM added two delayed feedback paths and a low-distortion feedforward path to the traditional NC structure to enable the NTF pole control, hence reducing the internal voltage swing and improving the linearity of the system. An Operational Transconductance Amplifier (OTA) reuse technique with a newly designed switched capacitor (SC) circuit is applied to share the two stages of the loop filter with only one amplifier, which lowers the power consumption of the DSM. The system is implemented in the TSMC 130nm CMOS process with a nominal 1.2V supply voltage for both the analog and digital subcircuits, occupying an active area of 1.2 !. Tested with an input of -2.9dBFS at 546.875Hz, the simulation shows a signal-to-noise-and-distortion ratio (SNDR) of 99.82dB, a signal-to-noise ratio (SNR) of 101.2dB and a spurious-free dynamic range (SFDR) of 105.1dB in a bandwidth of 10KHz, while consuming only 200 . The design achieved state-of-the-art Figure-of-merits (FoM) in all second-order DSMs reported with a Schreier FoM (SNDR) of 176.8dB and a Walden FoM of 125fJ/conv-step. The chip tape-out is ready and PCB fabrication is ongoing in preparation for in-lab measurement. This work has been accepted by the 2024 IEEE International Symposium on Circuits and Systems (ISCAS) for oral presentation.