Security risk evaluation for logic locking

• Main Author: Diao, Shengjia
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2024
• Subjects: Computer and Information Science; Engineering; Logic locking; Boolean satisfiability attack
• Online Access: https://hdl.handle.net/10356/177126
• Institution: Nanyang Technological University

The Integrated Circuit (IC) supply chain is facing multiple challenges as the globalization develops. Untrustworthy entities like chip manufacturers violated the intellectual properties and cause enormous economic loss. This circumstance highlights a necessity of robust logic obfuscation solutions to eliminate the dangers to the greatest extent and a comprehensive security evaluation system on those solutions keep abreast of the times. Boolean Satisfiability (SAT) attacks can almost break all existent logic obfuscation techniques. It is accepted as a powerful tool to assess the security of the logic obfuscation methods by the academia as well. However, the SAT attack faces significant challenges of logic locking on complex circuits, especially multipliers. In this report, we propose a novel SAT-based circuit preprocessing attack, named Xattack based on the concept of logic cones to enhance the efficacy of SAT attacks on complex circuits like multipliers. To enhance the efficiency of the SAT attacks on multiplier circuits, we partition the complex circuits into sub-circuits by logic cones, conducting SAT attacks on them iteratively. We analyze the reasons behind the significant resilience of multipliers and make comprehensive comparison between the SAT attack and proposed Xattack on ISCAS’85 benchmark circuits and 8-bit, 12-bit, 18-bit multipliers synthesized by ourselves. With 300 key gates inserted into the 18-bit multiplier, the result reported a reduction of over 1.5 million seconds, showcasing the superiority of our proposed method with an average 80% reduction in attacking time. This holds significant implications for strengthening efficiency of hardware security evaluation.