Multi-level diode clamped DC/AC inverter

• Main Author: Sia, Siow Hua.
• Other Authors: Luo Fang Lin
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Power electronics
• Online Access: http://hdl.handle.net/10356/17833
• Institution: Nanyang Technological University

Higher voltage rating of inverter can be achieved by connecting the power semiconductor devices in series. Among these series connection of power semiconductor devices, multilevel is one of the topology. Multilevel diode clamped inverter consists of series connected capacitors that divide DC bus voltage into a set of capacitor voltages, voltage across each capacitor is Vdc/(M-1), where Vdc is voltage of DC source, M is the level of inverter. An M-level inverter needs (M-1) capacitors. Multilevel inverter is able to achieve high quality output voltage (i.e. less total harmonic distortion, THD) by increase the number of level and select the appropriate switching angle. The multilevel inverters operate at fundamental frequency and this can reduce the switching loss as compare to pulse width modulation (PWM) inverter The main objective of this project is to investigate the best firing angles for different level of diode-clamped inverter and study the performance of multilevel diode clamped inverter. In overall, the proposed switching angle has been implemented and simulated by using PSIM 8.0. This report gives a detailed investigation and description of a multilevel inverter based on the fundamental switching frequency.