Design of a low-drop-out voltage regulator

• Main Author: Ong, Jian Cheng.
• Other Authors: Tan Meng Tong
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/17940
• Institution: Nanyang Technological University

This report describes the design of a Low-Drop-Out Voltage Regulator (LDO) with fast load transient response without a large external capacitor. The emphasis of the design is to reduce the overshoot and undershoot voltage of the load transient response while still maintaining a stable operating condition. LDO is a voltage regulator which regulates the output voltage with much smaller voltage drop across power transistor. LDO is popular for its low noise output and fast load transient response. It consists of an error amplifier, a Power PMOS transistor and a voltage reference. In most application, the LDO is usually loaded with an off-chip capacitor to maintain the stability and performance. However, with a smaller external capacitor, the output voltage usually experience a high voltage overshoot or undershoot during load transient response, thereby degrading the performance of the LDO. This project begins with the study of the LDO load transient response and stability identifying parameters and factors affecting the performance. A capacitor-free LDO with damping-factor-control (DFC) frequency compensation was adopted as the basic LDO structure for the design. Two techniques namely charge pumping and feed forward are subsequently introduced to improve the load transient response. The idea of employing the charge pump is to enable the LDO to provide more current to the load to reduce the undershoot voltage when there is a sudden demand in load current during load transient. The feed forward technique is used to improve the reaction time of the LDO when there is a sudden reduction in the demand for load current. This is achieved by reducing the voltage controlling the Power PMOS to reduce the supply current to the load, thereby reducing the voltage overshoot. Simulation was carried out in Cadence Spectre using CSM 0.18m CMOS process. From the simulation results, the load transient response of the LDO employing the two proposed techniques improves significantly and met all the design specifications.