CMOS PLA design

Complementary Metal Oxide Semiconductor (CMOS) digital integrated circuits are the enabling technology for the modern information age. Digital CMOS integrated circuits have been the driving force behind Very Large Scale Integration for high-performance computing and other scientific and engineering...

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Main Author: Dilparinder Singh
Other Authors: Lau Kim Teen
Format: Final Year Project
Language:English
Published: 2009
Subjects:
Online Access:http://hdl.handle.net/10356/18079
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-180792023-07-07T16:50:57Z CMOS PLA design Dilparinder Singh Lau Kim Teen School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering Complementary Metal Oxide Semiconductor (CMOS) digital integrated circuits are the enabling technology for the modern information age. Digital CMOS integrated circuits have been the driving force behind Very Large Scale Integration for high-performance computing and other scientific and engineering applications. The demand for digital CMOS ICs will be continually strong due to salient features such as low-power, reliable performance, circuit techniques for high speed such as using dynamic circuits and ongoing improvements in the processing technology. Programmable logic arrays (PLAs) which are used to realize the control logic circuits in CPU and DSP VLSI circuits form a very important building block of the CMOS VLSI systems. Several new configurations for the design of PLAs have been proposed in the literature recently. In this project, in-depth understanding of the digital integrated circuits and CMOS topics was attained and Virtuoso Schematic Capture and Spectre Simulation techniques were learnt through Cadence software. Simulations were carried out for different classes of CMOS Digital Integrated Circuits and also performance comparisons were done on various proposed PLA designs through Cadence simulations in terms of Speed and Power. Bachelor of Engineering 2009-06-19T06:30:56Z 2009-06-19T06:30:56Z 2009 2009 Final Year Project (FYP) http://hdl.handle.net/10356/18079 en Nanyang Technological University 140 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
Dilparinder Singh
CMOS PLA design
description Complementary Metal Oxide Semiconductor (CMOS) digital integrated circuits are the enabling technology for the modern information age. Digital CMOS integrated circuits have been the driving force behind Very Large Scale Integration for high-performance computing and other scientific and engineering applications. The demand for digital CMOS ICs will be continually strong due to salient features such as low-power, reliable performance, circuit techniques for high speed such as using dynamic circuits and ongoing improvements in the processing technology. Programmable logic arrays (PLAs) which are used to realize the control logic circuits in CPU and DSP VLSI circuits form a very important building block of the CMOS VLSI systems. Several new configurations for the design of PLAs have been proposed in the literature recently. In this project, in-depth understanding of the digital integrated circuits and CMOS topics was attained and Virtuoso Schematic Capture and Spectre Simulation techniques were learnt through Cadence software. Simulations were carried out for different classes of CMOS Digital Integrated Circuits and also performance comparisons were done on various proposed PLA designs through Cadence simulations in terms of Speed and Power.
author2 Lau Kim Teen
author_facet Lau Kim Teen
Dilparinder Singh
format Final Year Project
author Dilparinder Singh
author_sort Dilparinder Singh
title CMOS PLA design
title_short CMOS PLA design
title_full CMOS PLA design
title_fullStr CMOS PLA design
title_full_unstemmed CMOS PLA design
title_sort cmos pla design
publishDate 2009
url http://hdl.handle.net/10356/18079
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