Investigation of advanced low power digital IC design techniques
Low power digital circuits refer to the process of circuit design, through the adoption of various technologies and optimization measures to reduce the power consumption of the circuit, so that it consumes as little power as possible when performing digital operations and logic operations. Thi...
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| 格式: | Thesis-Master by Coursework |
| 語言: | English |
| 出版: |
Nanyang Technological University
2024
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/180990 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | Low power digital circuits refer to the process of circuit design, through the
adoption of various technologies and optimization measures to reduce the power
consumption of the circuit, so that it consumes as little power as possible when
performing digital operations and logic operations. This is particularly important
in modern electronic devices, especially portable devices (e.g., smartphones,
tablets, smartwatches, etc.), as well as large-scale integrated circuits (e.g.,
processors and memories), where low-power design can extend battery life, reduce
heat generation, and improve system reliability.
Circuit design and synthesis was done in Vivado using Verilog, followed by area
and power analysis using the simulation tool Design Complier based on SMIC
180nm library.
The analysis shows that although the designed low power 64-bit Carry Lookahead
Adder (CLA) has nearly six times the area of a conventional 64-bit CLA, it
successfully reduces the power consumption to about a quarter of that of a
conventional 64-bit CLA.
The analysis shows that although the designed low-power 64-bit CLA has nearly
six times the area of a conventional 64-bit CLA, it successfully reduces the power
consumption to 28.26% of that of a conventional 64-bit CLA." |
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