Design of low-quiescent low dropout regulator with sustainable performance

As System-on-Chip (SoC) applications in the Internet of Things (IoT) continue to grow, the demand for efficient power management has steadily increased. Low-Dropout Regulators (LDOs), as a vital element in power management systems, significantly influence SoC performance. A key area of current resea...

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Main Author: Lyu, Shuyang
Other Authors: Chan Pak Kwong
Format: Thesis-Master by Coursework
Language:English
Published: Nanyang Technological University 2024
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Online Access:https://hdl.handle.net/10356/181793
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-1817932024-12-20T15:47:51Z Design of low-quiescent low dropout regulator with sustainable performance Lyu, Shuyang Chan Pak Kwong School of Electrical and Electronic Engineering epkchan@ntu.edu.sg Engineering As System-on-Chip (SoC) applications in the Internet of Things (IoT) continue to grow, the demand for efficient power management has steadily increased. Low-Dropout Regulators (LDOs), as a vital element in power management systems, significantly influence SoC performance. A key area of current research on LDO regulators is the reduction of quiescent power consumption while maintaining good transient response. Moreover, with the rising level of SoC integration, capacitorless LDOs (OCL-LDO regulators) have become increasingly popular in SoC applications. This project presents a low-power Level Shift Flipped Voltage Follower (LSFVF) capacitorless LDO regulator, which is designed using the TSMC 40nm Process Design Kit (PDK). The design incorporates a dynamic cascode biasing circuit to enhance transient response. By replacing the single control transistor in the LSFVF with composite cascode transistors, the loop gain of the LSFVF is increased, leading to improved line and load regulation, as well as enhanced accuracy of the LDO regulator. Additionally, employing a 2-stage operational amplifier (opamp) instead of a 1-stage symmetrical operational transconductance amplifier (OTA) for the control circuit, it enhances the reference voltage tracking capability, further improving regulation performance. The simulation results using Cadence tools demonstrated that, with an input voltage of 1.2V, the dropout voltage is 200mV, and the quiescent current under no-load conditions is 768.2nA. For a 50pF load capacitor, under a 0-10mA load current and a 1µs edge time, the value for the overshoot is obtained as 31.22 mV, while the undershoot reaches 75.48 mV, and the settling time to 1% accuracy is 595µs. Master's degree 2024-12-18T13:04:50Z 2024-12-18T13:04:50Z 2024 Thesis-Master by Coursework Lyu, S. (2024). Design of low-quiescent low dropout regulator with sustainable performance. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/181793 https://hdl.handle.net/10356/181793 en application/pdf Nanyang Technological University
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering
spellingShingle Engineering
Lyu, Shuyang
Design of low-quiescent low dropout regulator with sustainable performance
description As System-on-Chip (SoC) applications in the Internet of Things (IoT) continue to grow, the demand for efficient power management has steadily increased. Low-Dropout Regulators (LDOs), as a vital element in power management systems, significantly influence SoC performance. A key area of current research on LDO regulators is the reduction of quiescent power consumption while maintaining good transient response. Moreover, with the rising level of SoC integration, capacitorless LDOs (OCL-LDO regulators) have become increasingly popular in SoC applications. This project presents a low-power Level Shift Flipped Voltage Follower (LSFVF) capacitorless LDO regulator, which is designed using the TSMC 40nm Process Design Kit (PDK). The design incorporates a dynamic cascode biasing circuit to enhance transient response. By replacing the single control transistor in the LSFVF with composite cascode transistors, the loop gain of the LSFVF is increased, leading to improved line and load regulation, as well as enhanced accuracy of the LDO regulator. Additionally, employing a 2-stage operational amplifier (opamp) instead of a 1-stage symmetrical operational transconductance amplifier (OTA) for the control circuit, it enhances the reference voltage tracking capability, further improving regulation performance. The simulation results using Cadence tools demonstrated that, with an input voltage of 1.2V, the dropout voltage is 200mV, and the quiescent current under no-load conditions is 768.2nA. For a 50pF load capacitor, under a 0-10mA load current and a 1µs edge time, the value for the overshoot is obtained as 31.22 mV, while the undershoot reaches 75.48 mV, and the settling time to 1% accuracy is 595µs.
author2 Chan Pak Kwong
author_facet Chan Pak Kwong
Lyu, Shuyang
format Thesis-Master by Coursework
author Lyu, Shuyang
author_sort Lyu, Shuyang
title Design of low-quiescent low dropout regulator with sustainable performance
title_short Design of low-quiescent low dropout regulator with sustainable performance
title_full Design of low-quiescent low dropout regulator with sustainable performance
title_fullStr Design of low-quiescent low dropout regulator with sustainable performance
title_full_unstemmed Design of low-quiescent low dropout regulator with sustainable performance
title_sort design of low-quiescent low dropout regulator with sustainable performance
publisher Nanyang Technological University
publishDate 2024
url https://hdl.handle.net/10356/181793
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