Improved inter integrated circuit bus verification based on universal verification methodology

• Main Author: Jiang, Zhuoyuan
• Other Authors: Kim Tae Hyoung
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2025
• Subjects: Engineering; Verification; UVM; I3C
• Online Access: https://hdl.handle.net/10356/182757
• Institution: Nanyang Technological University

Nowadays, with the development of integrated circuits, many smart devices such as smart phones and computers with a wide variety of functionalities are developed. As a smart device might contain many chips including sensors, CPU, GPU and memory, protocols are required to establish communication among these chips. The I2C protocol is an industry proven protocol widely used to connect CPU with peripheral devices including sensors. However, because of the increasing need for low power consumption and high performance in integrated circuits, the I2C interface is gradually reaching a bottleneck. To solve this problem, I3C, an improved version of I2C which is much faster and consumes less power is developed. Due to the increasing complexity of integrated circuits, the difficulty of verification increases sharply. Therefore, efficient and convenient verification methods should be developed. In this project, a verification platform with I3C master BFM that can simulate performance of I3C master is built using System Verilog and UVM to verify design of an I3C slave block. The whole verification process is completed, including making verification plans, deciding testing points, building verification platform, designing testcases for verification and collecting coverage. Cadence IES and IMC tools in Linux system are used to complete these tasks. The functional coverage of around 93.69% and code coverage of around 87.58% is achieved, which proves the effectiveness of the design. All functions of the I3C slave block are tested and verified to meet verification requirements.