An ultra-low voltage 40nm CMOS current reference with low temperature coefficient
This dissertation presents a low-power and low-voltage subthreshold current reference without the use of bandgap reference topology and amplifier. Implemented in TSMC40nm process technology, the proposed topology works stably at 0.65V supply, outputting a low T.C. current reference. The circuit empl...
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis-Master by Coursework |
| Language: | English |
| Published: |
Nanyang Technological University
2025
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/182765 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This dissertation presents a low-power and low-voltage subthreshold current reference without the use of bandgap reference topology and amplifier. Implemented in TSMC40nm process technology, the proposed topology works stably at 0.65V supply, outputting a low T.C. current reference. The circuit employs piecewise temperature compensation to achieve lower temperature coefficient. A low temperature coefficient of 21.58 ppm/℃ at tt corner can be obtained. For Monte-Carlo simulation of 100 samples, the mean T.C. is 39.55 ppm/℃ and the process sensitivity is 8.3% for the range of -20-80℃. This shows good immunity against process variation. Besides, the topology exhibits low power consumption of only 91nW. Finally, the line sensitivity is acceptable and the FOM is reasonable when compared with other reported works. In general, with its low supply voltage, low power and low T.C., the proposed work is suitable for portable or implantable medical applications with strict requirement and IoT circuits and systems. |
|---|