Design and implementation of HBM-enhanced RecoNIC with RDMA control offloading and UDP packet generation

• Main Author: Pu, Zihao
• Other Authors: Goh Wang Ling
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2025
• Subjects: Engineering; RDMA; RoCEv2; SmartNIC; HBM; FPGA; Direct memory access
• Online Access: https://hdl.handle.net/10356/182970
• Institution: Nanyang Technological University

This dissertation delves into the enhancement of Remote Direct Memory Access enabled (RDMA-enabled) Smart Network Interface Card (SmartNIC) technology, with a particular focus on the RecoNIC platform, to address existing limitations and propel advancements in integrated circuit design. In the context of the growing demand for distributed systems driven by the rapid expansion of large language models (LLMs) and their applications, this research explores the integration of High Bandwidth Memory (HBM) as a replacement for the current DDR4 memory. This strategic shift aims to unlock greater on-board computational capabilities and mitigate memory bandwidth constraints, which are critical for supporting complex on-board computing pipelines. The study also emphasizes the development of a flexible control offload engine designed to expedite communication processes, thereby enabling hardware-initiated RDMA communication without the need for software intervention. This innovation is crucial for enhancing the scalability and software compatibility of SmartNICs, paving the way for more efficient distributed computing solutions. Furthermore, the dissertation introduces a User Datagram Protocol (UDP) packet generation module, which significantly augments the SmartNIC's ability to generate and communicate with remote devices. By examining the trade-offs between various SmartNIC architectures, including ASIC-based, programmable, and FPGA-based solutions, this work provides valuable insights into the design considerations and challenges inherent in SmartNIC technologies. The research underscores the importance of balancing performance and flexibility in SmartNIC design, offering guidance for developing more adaptable and efficient solutions to meet the evolving demands of distributed computing and software-defined infrastructures. Ultimately, the findings contribute to the advancement of SmartNIC solutions, laying the groundwork for future innovations in the field and promoting the development of high-performance, flexible, and scalable networking applications.