Development of a power-efficient low-cost cryptosystem for secured embedded systems

• Main Author: Pua, Yi Cheng.
• Other Authors: Patra Jagdish Chandra
• Format: Final Year Project
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Computer science and engineering::Computer systems organization::Performance of systems
• Online Access: http://hdl.handle.net/10356/18915
• Institution: Nanyang Technological University

As internet connectivity becomes more and more ubiquitous and the number of embedded devices that are able to connect to the internet keeps on growing, it is imperative that these devices are able to achieve a level of cryptographic security comparative to that of a desktop computer in order to perform transactions which require cryptographic protection, for example Internet Banking and online shopping. The processors currently used in embedded devices are designed with energy efficiency in mind and are simply not powerful enough to handle commonly used cryptographic operations satisfactorily. In our project, we aim to design and fabricate a power-efficient low-cost cryptographic co-processor for elliptic curve cryptography (ECC), more specifically, ECC using binary finite fields as a basis. By using a separate chip to perform cryptographic operations, this co-processor can be turned on only when needed, and turned off to save power otherwise, thus ensuring reasonable battery life. One of the most widely used and costly operation on finite fields is the multiplication operation. In this project, we investigate and implement existing binary finite field GF(2m) multipliers using FPGAs, as well as suggesting improvements to the bit-serial and digit-based designs, resulting in significant advantages over those currently available. Our work focuses on 233-order multipliers and uses the NIST recommended trinomial as the polynomial basis for the multiplier. By using a suitable elliptic curve over this field, a cryptosystem that is similar in cryptographic strength to 112-bit Triple-DES can be built. Apart from trinomial basis multipliers, redundant representation multipliers are also implemented and compared against our design to show the advantages and practicality of our design.