Profile driven schemes for energy-sensitive cache hierarchy
With the advent of mobile and handheld devices, power consumption in embedded systems has become a key design issue. Of the components that consume significant amounts of power in an embedded system, cache memories have been reported to consume in excess of 40% of the total power in typical high end...
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| 格式: | Theses and Dissertations |
| 語言: | English |
| 出版: |
2009
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/19286 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | With the advent of mobile and handheld devices, power consumption in embedded systems has become a key design issue. Of the components that consume significant amounts of power in an embedded system, cache memories have been reported to consume in excess of 40% of the total power in typical high end embedded processors. Therefore, cache memories are an obvious target of many low-power optimizations. Recently, it has been shown that cache requirements of the applications vary widely and a significant amount of energy spent in cache accesses can be saved by tuning the cache parameters according to the needs of the application. However, tuning the cache memory to suit the needs of the application entails identification of optimal cache configurations in the first place. With the large set of configurations to choose from, this process is prohibitively time consuming if done through exhaustive cache hierarchy simulations. Therefore, there exists a need for tools that can rapidly identify optimal cache configurations to tune the cache parameters for any given application. |
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