ATM switching architecture for broadband-ISDN and its performance

• Main Author: Zhu, Li Qiang.
• Other Authors: Tan, Chee Heng
• Format: Theses and Dissertations
• Language: English
• Published: 2009
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Wireless communication systems
• Online Access: http://hdl.handle.net/10356/19748
• Institution: Nanyang Technological University

Owing to the unscheduled nature of cell arrivals to an ATM switch, two or more cells may arrive at different input ports in one time slot and be destined to the same output port. The ATM switch may allow one or more of these cells to pass through simultaneously to reach the output ports while the other cells may have to be queued for later slots or have to be discarded, depending on the buffering schemes. In this project, a model to represent the cell traffic at the input ports as well as a cell selection policy is chosen. A simple ATM switch architecture is proposed, and its performance is simulated and analyzed in terms of utilization, throughput, cell loss probability, and cell delay versus buffer and switch sizes.