VLSI efficient architectures for triple moduli based RNS computations
In this research work, we have made a thorough evaluation of existing contributions on the reverse converters based on the triple moduli and proposed new reverse converters and architectures. In addition, we have proposed reverse converters for new moduli sets in an attempt to realize VLSI efficient...
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sg-ntu-dr.10356-23792023-03-04T00:45:28Z VLSI efficient architectures for triple moduli based RNS computations Cao, Bin Thambipillai Srikanthan School of Computer Engineering DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures In this research work, we have made a thorough evaluation of existing contributions on the reverse converters based on the triple moduli and proposed new reverse converters and architectures. In addition, we have proposed reverse converters for new moduli sets in an attempt to realize VLSI efficient alternatives. DOCTOR OF PHILOSOPHY (SCE) 2008-09-17T09:01:32Z 2008-09-17T09:01:32Z 2006 2006 Thesis Cao, B. (2006). VLSI efficient architectures for triple moduli based RNS computations. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/2379 10.32657/10356/2379 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures Cao, Bin VLSI efficient architectures for triple moduli based RNS computations |
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In this research work, we have made a thorough evaluation of existing contributions on the reverse converters based on the triple moduli and proposed new reverse converters and architectures. In addition, we have proposed reverse converters for new moduli sets in an attempt to realize VLSI efficient alternatives. |
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Thambipillai Srikanthan |
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Thambipillai Srikanthan Cao, Bin |
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Theses and Dissertations |
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Cao, Bin |
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Cao, Bin |
title |
VLSI efficient architectures for triple moduli based RNS computations |
title_short |
VLSI efficient architectures for triple moduli based RNS computations |
title_full |
VLSI efficient architectures for triple moduli based RNS computations |
title_fullStr |
VLSI efficient architectures for triple moduli based RNS computations |
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VLSI efficient architectures for triple moduli based RNS computations |
title_sort |
vlsi efficient architectures for triple moduli based rns computations |
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2008 |
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https://hdl.handle.net/10356/2379 |
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1759854887825309696 |